1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and, more particularly, to a semiconductor package and a fabrication method thereof for improving the product reliability.
2. Description of Related Art
Semiconductor packaging technologies have been continuously improved to meet the miniaturization requirement of electronic products. A semiconductor package generally includes a packaging substrate, a semiconductor chip disposed on the packaging substrate, an encapsulant encapsulating the semiconductor chip, and a plurality of solder balls for an electronic device to be electrically connected thereto. As such, the overall thickness of the semiconductor package includes the thickness of the encapsulant, the thickness of the packaging substrate and the height of the solder balls. Therefore, reducing the thickness of the packaging substrate has become an important factor to reduce the size of the semiconductor package.
Conventionally, a core layer is formed in the packaging substrate for improving the rigidity of the overall structure, thereby facilitating subsequent chip bonding and encapsulation processes. However, the core layer increases the thickness of the packaging substrate and results in an increased height of the overall package structure.
Accordingly, coreless packaging substrates are developed to meet the miniaturization requirement. FIGS. 1A to 1C are schematic cross-sectional views showing a fabrication method of a semiconductor package 1 as disclosed by U.S. Pat. No. 7,795,071.
Referring to FIG. 1A, a coreless packaging substrate la is formed on a carrier (not shown) and then the carrier is removed. The coreless packaging substrate la has an insulating protection layer 14 and a circuit layer 13 embedded in the insulating protection layer 14. A lower surface of the circuit layer 13 is flush with a lower surface of the insulating protection layer 14, and an opposite upper surface of the insulating protection layer 14 has a plurality of openings 140 formed therein for exposing a portion of an upper surface of the circuit layer 13.
Referring to FIG. 1B, at least a semiconductor chip 17 is disposed on the lower surface of the insulating protection layer 14 and electrically connected to the circuit layer 13 through a plurality of conductive bumps 170.
Referring to FIG. 1C, a surface finish 12 is formed on the exposed portion of the circuit layer 13 in the openings 140.
By dispensing with a core layer, the fabrication cost and time of the packaging substrate 1a are reduced. On the other hand, the packaging substrate 1a has reduced rigidity due to its reduced thickness. Therefore, the packaging substrate 1a can easily crack during a subsequent chip bonding or encapsulation process, thereby reducing the product yield and reliability.
Further, after the carrier is removed, warpage can easily occur to the packaging substrate 1a so as to cause delamination between the circuit layer 13 and the insulating protection layer 14. As such, the packaging substrate 1a must be discarded, thus increasing the material cost.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.